MEMS silicon wafer thinning, backlapping and polishing
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Ultra-Thin  

Lapping, backlapping, thinning and polishing of MEMS, silicon and other semiconductor materials in prototype and production quantities. Customer supplied wafers in sizes up to 12" diameter, can be lapped on one or both sides. Finished singulated dice can be thinned to 100 microns or less without edge deterioration.

During backlapping, the circuit side of the wafer or diced chip can be protected by various compatible processes. The finished wafers can be returned in wafer boats or even mounted on individual carriers for further processing by the customer. Thickness tolerances as close as ±0.0001" are possible, and parts can be lapped to as thin as 0.001 inches.

If your needs include MEMS, SOI, SDB, WDB or CMP, Valley may have the right process to resolve your specific requirements.

Information on other related processes:
· www.ultra-thin.com/mems.htm 
MEMS and bonded SOI ultra-thin Silicon wafers
· www.siliconwafers.net/thinned.htm 
Silicon wafers thinned to produce thinner dice-chips
· www.valleydesign.com/pr8.htm 
Polished glass wafers and substrates to SEMI standards
· www.ultra-thin.com/thin-optics.htm 
Thin optical glass windows, wafers, plates and sheets

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Updated: 15 April 2008
 
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Valley Design West Valley Design East
151-D Harvey W. Blvd., Santa Cruz, CA 95060 Two Shaker Road, Bldg. E-001, Shirley, MA 01464
Tel: 831-420-0595  Fax: 831-420-0592 Phone: 978-425-3030  Fax: 978-425-3031
Email:west@valleydesign.com Email:east@valleydesign.com
© 2008 Valley Design Corp. All Rights Reserved
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